The address in space of data is appropriated to each register, they on the first 32 cells of the RAM. Though the register file physically out of the RAM, the similar organization of memory gives flexible access to. The registers X, Y and Z can be used for indexation of any register. Except usual functions, the registers RR31 have additional functions, these registers can be used as address indexes in of memory of data. These registers are designated as X,Y,Z and are defined as follows:
ALU of the processor is directly connected to 32 registers of general purpose. For one machine cycle of ALU makes operations between of the register file. The ALU teams are divided into three main - arithmetic, logical and bit.
When the program counter is installed on the current vector of a for its processing, the corresponding flag generated by a hardware is dumped. Some flags of interruption can be dumped by record of logical unit in bit corresponding to a flag.
The register file of fast access contains 32 8-digit of general purpose access to which is provided for one machine cycle. Therefore for one machine cycle one operation ALU is executed. Two operands get out of the register file, operation is carried out, it registers in the register file - all for one machine cycle.
At the appeal to memory five various modes of an are used: direct, direct with shift, direct, with preliminary decrement and direct with a. Regista RR31 of the register file are used as indexes for direct addressing. Direct addressing has access to all memory of data. Direct addressing with shift is used for access to 63 cells which basic address is set by contents of the registers Y or Z.
All teams operating with registers directly are addressed to any of registers for one machine cycle. The only exception - five teams operating with the constants SBCI, SUBI, CPI, ANDI, ORI and the LDI team loading the register a constant. These teams work only with the second half of the register file - RR3 of the SBC, SUB, CP, AND and OR Team, also as well as all others, are applicable to all register file.
AT90S2333/4433 contain 128/256 bytes electrically of the erased memory (EEPROM). EEPROM is organized as separate data which each byte can be read and rewritten. EEPROM maintains not less than 100000 cycles of record/deleting. Access to non-volatile memory of data is considered below and is set by registers of the address, data and management. Further loading of data in EEPROM through SPI will be considered.
Six of 32 registers can be used as three 16-digit indexes in address space of data that gives the chance to highly effective address arithmetics (the 16-digit registers X, Y and Z). One of three address indexes (register Z) can be for addressing of tables in memory of programs.
By means of teams of relative transitions and a call of subprogrammes access to all address space is provided. The most part of the AVR teams has the size 16 of categories, one word. Each address supports one in memory of programs 16-or 32-bit team.
Bit 2-N: Flag of negative result. This flag displays result of various arithmetic and logical operations. In more detail about it it is possible to read in the description of system of teams.
Bit 6-T: Storage of the copied bit. Teams of copying of bits of BLD (Bit LoaD) and BST (Bit STore) use this bit as a source and a of the processed bit. The bit from the register of the register file can be copied in T BST team, the bit of T can be copied in bit of the register file by the BLD team.
Bit 4-S: the bit of a sign, S = is always equal to N XOR of Bits of S excluding OR between N flags (negative result) and V (overflow of a to two). In more detail about it it is possible to read in the description of a of teams.
External dumping is processed on low level on RESET conclusion. The conclusion has to keep in a low state at least two periods of clock frequency. After achievement of tension of Vrst the delay timer is started, through Tout period the processor is started.